1. Field of the Invention
The embodiments of the invention generally relate to integrated circuit structures and, more particularly, to an integrated circuits structure that incorporates multiple stacked chevron non-planar field effect transistors (FETs) and a method of forming the integrated circuit structure.
2. Description of the Related Art
As transistor design is improved and evolves, the number of different types of transistors continues to increase. Multi-gated non-planar metal oxide semiconductor field effect transistors (FETs), including dual-gate non-planar FETs (e.g., finFETs) and tri-gate non-planar FETs, were developed to provide scaled devices with higher drive currents and reduced short channel effects over planar FETs.
Additionally, the mobility of charge carriers in FET channel regions can be optimized for different types of FETS (i.e., n-type FETs (NFETs) or p-type FETs (PFETs)) as a function of the semiconductor crystalline orientation. Specifically, in a PFET, hole mobility can be optimized and transistor switching delay can be minimized by forming the channel region with a semiconductor having a [110] crystalline orientation. Contrarily, in an NFET, electron mobility can be optimized and delay can be minimized by forming the channel region with a semiconductor having a [100] crystalline orientation. To that end, U.S. Pat. No. 6,794,718, issued to Nowak et al. on Sep. 21, 2004 and incorporated herein by reference, discloses a complementary metal oxide semiconductor (CMOS) structure that comprises a fin-type NFET having an n-channel in a semiconductor fin with a [100] orientation and a fin-type PFET having a p-channel in a semiconductor fin with a [110] orientation. The [100] and [110] orientation semiconductor fins are formed on the same substrate, but are positioned with a non-orthogonal, non-parallel orientation with respect to one another (i.e., a chevron structure) in order to achieve the different crystalline orientations. Gates are then formed (i.e., lithographically patterned) across the fins such that the semiconductor fin(s) of completed FETs are positioned at a non-perpendicular angle with respect to the gates. See also U.S. Pat. No. 6,867,460 issued to Anderson et al. on Mar. 15, 2005 and incorporated herein by reference, which discloses a static random access memory (SRAM) cell with chevron finFET logic.
As mentioned above, non-planar FETs (e.g., finFETs or trigate FETs) were developed to provide scaled devices over planar FETs. The scaled devices generally allowed semiconductor products to be produced with an even greater CMOS device density (i.e., a greater number of stacked transistors in a given area) over those prior art semiconductor products that included CMOS devices with only planar FETs. Also as mentioned above, chevron CMOS devices (i.e., CMOS devices with non-planar FETs having angled semiconductor fins) were developed to optimize device performance. However, if multiple stacked non-planar FETs are formed with a chevron configuration with a current minimum lithographic contacted-gate pitch and a current minimum lithographic fin pitch, mismatch of the contacted-gate pitch and the fin pitch inevitably results.